Network elements in existing transport networks serve for establishing semi-permanent (“cross”)connections in the network. Such network elements include crossconnects and add/drop multiplexers. For crossconnecting high bitrate digital signals, it is advantageous to use a synchronous switch matrix. While today transport networks rely basically on the Synchronous Digital Hierarchy (SDH, ITU-T G.707), a new Optical Transport Hierarchy has been defined in ITU-T G.709, where the transport signals are no longer synchronous but asynchronous within a predetermined range of ±20 ppm from a nominal frequency.
Even when the transport signals are not synchronous, a synchronous switch matrix may nonetheless be used, if all payload channels are mapped internally into an common synchronous rate which is higher than the highest payload channel rate. Rate adaptation to the internal rate will be performed by bit stuffing. At the output of the network elements, however, the payload channels must then be de-mapped from the internal rate signal and the stuff bits removed. This will cause non-isochronous bit streams that represent the respective payload channels, since the bit clock of a bit stream has gaps from the removed stuff bits. Therefore, a narrow band phase lock loop (PLL) would be required at each payload channel for converting the non-isochronous bit stream back to an isochronous bit stream. Tight output jitter requirements would apply to this function.
Moreover, in certain applications, it would be advantageous if a network element would be able to process transport signals of different types. For instance, transmission equipment for payload bit rates in the Giga-bit range often provides as an option forward error correction (FEC) to the transport signals. The equipment needs therefore the ability to operate at different bit rates, i.e., with or without FEC, on the basis of configuration. On the other hand, it would be advantageous to provide the capability to process SDH and OTH type signals within the same equipment. For such applications, the bit rates must be accommodated to the actually used signal type, which might become very complex for narrow band PLLs at the outputs a network element. Clock circuits with a low Q factor could provide an automatic bit rate accommodation capability with in a range of ±10% with a single oscillator circuit only. High Q clock circuits, however, would require a separate crystal oscillator for each particular bit rate. A clock filter circuit for destuffed non-isochronous transport signals would hence require a particular voltage controlled crystal oscillator (VCXO) for every payload channel and for every bit rate.
It is therefore an object of the present invention, to provide a simplified clock circuit that can be configured to operate at least at two different bit rates.